The present invention relates to a semiconductor memory device, and more particularly, to an improved word line and driver structure for a dynamic random access memory with an open bit line structure.
Semiconductor memory devices are highly integrated; consequently, the most frequently adopted method for increasing the chip density within a restricted area is to minimize the size of the memory cell which includes one storage capacitor for storing data and one access transistor for transferring the data through bit lines. This however, causes a reduction of the pitch of the bit lines and the pitch of the word lines for selecting the memory cells, where the pitch is defined as the space between the lines. The area on which bit line selectors, bit line selection drivers, word line selectors, and word line selection drivers are arranged may be concomitantly and undesirably reduced however, thereby causing numerous problems. Generally, word line drivers are directly related to the sensing operation for the transfer of data by controlling the access transistor of the memory cell; accordingly, effective design and layout of the word line drivers is very important.
In a conventional folded bit line structure each of the word lines is coupled to a corresponding word line driver. The number of word line selectors is proportional to the number of the word line drivers with one word line selector connected to four word line drivers. The word lines in a group are connected to corresponding word line drivers, and the word line drivers are each controlled by a word line selector that is, in turn controlled by a word line selection signal. Such a conventional structure is difficult to design and layout in a semiconductor memory device using a design rule appropriate for design at a sub-micron level (e.g., for a very large scale integration memory device over the 64 megabyte level) of a dynamic random access memory. Furthermore, an increase in the density of the memory device lo requires reduction of the pitch between the word lines, thereby increasing the word line resistance. The word lines effect each other by noises generated from adjacent word lines which have their own specific resistances and junction capacitances.
A conventional semiconductor chip usually has first metal resistances arranged in parallel with the word lines. The width of the word lines, made of layers of polysilicon forming the gate electrodes of the single transistor memory cells, has been gradually reduced to obtain an increase in the density of the chip, thereby causing increased line resistance since resistance of the word line is inversely proportional to the width of the word line. A strap region indicates a region where a substance such as metal is arranged in the word lines, (i.e., strapped over a given length) in order to minimize the delay time of a transfer signal via the word lines. In addition, the word line resistances increase in proportion to the number of word lines on the chip, which consequently decreases the speed at which data stored in the memory cells may be sensed.